Write a clock in verilog language?
Verification Manager Interview Questions
3,712 verification manager interview questions shared by candidates
Basic questions related to Digital design, Verilog, specific protocol, Systemverilog, OOPS, UVM and apptitude.
How do you ensure that your verification test plan provides complete coverage for a complex SoC design, and what steps do you take when coverage goals are not being met?
Amazon principles and related information.
Questions for python program, like regular expression
explain last project
Gave me a scenario and asked to develop a test plan to best verify the design.
electronics and C, some measurement knowledge
When you run a simulation of 16ms, the simulation could take much longer (like 1hour) on a computer. Why?
Codice UVM e codice VHDL
Viewing 191 - 200 interview questions