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Verification Engineer Interview Questions
3,718 verification engineer interview questions shared by candidates
Transfer function of a simple VCO
Describe your task and what you achieved in your project?
What is your ultimate goal with Valley?
A data vs clock path is given and there is latency in one of them how would you current it
Basics of Digital Electronics, Logic Design, Computer Architecture, FPGA, Verilog, SystemVerilog, UVM, some communication/bus protocols, Projects explanation.
What do you know about ARM and specifically about their products?
What are the 1st two lines of codes in a typical UVM test?
Basics of computer architecture, Functional coverage, C++ and some advanced Virtual Memory Subsystem concepts.
Virtual Memories..
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