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Design Verification Engineer Interview Questions
3,712 design verification engineer interview questions shared by candidates
write a code,a task to fill an array[x][y] ?
The first team I interviewed with asked about: Computer architecture basics: Pipelines, branching and hazards, and hardware-based computer organization themed questions. The questions were along the lines of: 1) Tell me about the performance implications of a deep pipeline. 2) What do "volatile" and "virtual" mean in programming? 3) Define RISC vs. CISC differences. They also asked questions on course work in progress, completed, and projects listed on my resume. The second interview team was more behavioral, asking questions about projects and coding experiences.
How do you verify this logic block?(a black box with some input and outputs and the timing diagram is given
They asked detailed questions about memory and interconnect design in advanced systems. They also gave me a small assignment which I had to do online.
Verification of a processor core - caches/interrupt etc
Questions about UVM, computer architecture, C++ coding and background.
Tell me about your background What are your aspirations in life? Why would you like to work with such a company? Tell us about an experience where you used your skills in your previous job.
Basic sv and uvm concepts
How long was I processing insurances in my previous positions, was I comfortable with commuting the first month for training? If I've heard of Smile brands or Monarch dental before? What I was wanting in a position, how much would I would like my rate of pay to start at. How I work out conflicts or issues within the workplace.
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