-General digital flow design -General UVM verification questions
Design Verification Engineer Interview Questions
3,712 design verification engineer interview questions shared by candidates
How do you verify this logic block?(a black box with some input and outputs and the timing diagram is given
General discussion on my coding background and course work
Why is MOESI better than MESI
The first team I interviewed with asked about: Computer architecture basics: Pipelines, branching and hazards, and hardware-based computer organization themed questions. The questions were along the lines of: 1) Tell me about the performance implications of a deep pipeline. 2) What do "volatile" and "virtual" mean in programming? 3) Define RISC vs. CISC differences. They also asked questions on course work in progress, completed, and projects listed on my resume. The second interview team was more behavioral, asking questions about projects and coding experiences.
Tell me about yourself?
explain ASIC flow
already sv is there.... why UVM required??
explain about UVM TB architecture? explain what is UVM factory
Question on Project, tool awareness, uvm methodology, driver code and testplan development.
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