There were 4 rounds - 3 technical and 1 HR.
Design Verification Engineer Interview Questions
3,720 design verification engineer interview questions shared by candidates
Write a logic to find a maximum number among the three given numbers.
Pipelining, Cache, Virtual memory, Compilation steps, C keywords Verification Concepts- SystemVerilog, Assertions, UVM
Systemverilog assertions and constraints questions
Just telephone conversation but it is very bad mention in the website and doing something different. So please be aware such fraud or HR person who is not what they said in applicaitons.
What is your experience with random constrained stimulus?
completely based on system verilog and digital design concepts
what kind of work you want to do for next 2-3 yrs?
Assembly and C programming exercises
Related to flip flops, chaining time, response time, setup/hold time etc
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