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Design Verification Engineer Interview Questions
3,720 design verification engineer interview questions shared by candidates
System Verilog design of a RAM module according to set specification.
Explain pair-wise testing
When in your previous work did you wish you behaved differently?
How instructions are executed in assembly language? How data is transferred between cpu and cache? Why we need cache, why we don't use main memory? Why cache size is kept small?
Develop a C algorithm to solve arbitration in bus
Explain your role on this project / job.
What is the difference between C and C++?
crazy nonsense questions. How do you measure voltage of the wave from modelsim in gtkwave.? each question on each word in resume.
4. explain interrupt handling, and various scenarios
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