Questions related to Pipelining, Interrupt Handling.
Asic Verification Engineer Interview Questions
273 asic verification engineer interview questions shared by candidates
Write constraints for unique elements in an array. Write assertions for different scenarios of AXI protocol. Basics of UVM including testbench components, phases, TLM ports.
Questions on protocols like API, AXI, AHB, API, UART.
1)Driver sequencer handshake.
* job experience and roles * how do u verify a scheduler * A block has inputs of network pkts and buffers/pipelines them through an RTL. RTL has counters which will tell how many packets are sent. How to verify? (Counters Read => count. Write => clear) How to verify counts? what cases will u test? * Given a sys verilog code for a memory model and asked to implement read/write/move functions and write checks
Systemverilog and UVM questions
what do u know about virtual pages
Question regarding Logic design, Verilog ,State Machine- pattern detection, Comp Arch- Pipeline, hazards, cache, associativity, Basic Perl were asked.
I can't say exactly but one SystemVerilog question was to implement a finite state machine given a certain output. Review sequence detectors.
Constraint randomization based question linking to AXI and memory filling
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