Hardware Asic Design Engineer Interview Questions

12 hardware asic design engineer interview questions shared by candidates

1.Inverted temperature effect on STA. the question was based on temperature effects on delay below 65nm technology. how STA works under those conditions at different corners. 2. An interesting question about how latency affects jitter. 3. Maximums kew allowed when lock up latches are used. 4. OCV n questions based on it. 5. CRPR. 6. how does a cell get min n max delay? 7. spef file contents, questions about star-rd extractor working. 8. Internship exp based questions.
Nov 8, 2013

1.Inverted temperature effect on STA. the question was based on temperature effects on delay below 65nm technology. how STA works under those conditions at different corners. 2. An interesting question about how latency affects jitter. 3. Maximums kew allowed when lock up latches are used. 4. OCV n questions based on it. 5. CRPR. 6. how does a cell get min n max delay? 7. spef file contents, questions about star-rd extractor working. 8. Internship exp based questions.

Using basic gates to build a full adder. Draw FSM and how to verify it using C. Also many C/C++ questions and computer architecture questions. And give you some clock diagram and ask what component will result in that diagram. Overall not very easy questions.
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ASIC Hardware Intern

Interviewed at Qualcomm

3.8
Mar 3, 2016

Using basic gates to build a full adder. Draw FSM and how to verify it using C. Also many C/C++ questions and computer architecture questions. And give you some clock diagram and ask what component will result in that diagram. Overall not very easy questions.

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