Why you do clk gating in your design
Asic Physical Design Engineer Interview Questions
38 asic physical design engineer interview questions shared by candidates
How to determine which register you want to gate in netlist ?
How often do you use the digital programming software?
Static Timing Analysis, Setup time, Hold time, Clock gating, Clock Path Pessimism Removal, Digital design flow, Vmin
What is setup time and hold time? How would you fix these violations pre-silicon and post-silicon? What is the difference between clock skew, clock jitter, and clock uncertainty? Draw CMOS for a 1-input NOT gate, 2-input NOR gate, and 4-input NAND gate. Draw the circuit for a full-adder with minimal number of gates.
mentioned above
How is uncertainty determined.
they ask the inputs into the tools for different steps of physical design.
Tell any 5 commands and how to validate floorplan
Question on power optimization technique beyond what the tools have options, basically looking for some innovative way of power optimization.
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