How to design an 64 bit adder if only given a 32 bit adder. After you design it, you will be asked how to verify it. The verification maybe related to SystemVerilog.
Asic Engineer Interview Questions
1,316 asic engineer interview questions shared by candidates
Design a state machine to detect bit sequence. How do you verify it?
How to make nor gate using two input mux
Personal research, DVFS, CDC, metastable, asynchronous FIFO, synchronizer, level shifter, clock gating, power gating, dynamic power, leakage power.
how to avoid overflow in FIFO design; design a FSM for bit string detect
all about resume, STA, DFT, Pipelining
Going over the resume in detail
Synchronous ans Asycnchronous FIFO design and verification.
Write the code of a synchronous FIFO,
The difference between blocking and non-blocking statements
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