mostly regular
Asic Engineer Interview Questions
1,316 asic engineer interview questions shared by candidates
Describe the 5 stages in MIPS pipeline structure.
verilog basic, C++,C basics
fifo design
how abot time borrowing in Latch,Tell us about clock control and why it can be done
The phone screen with basic questions like your visa status.
I report only the technical questions: - how the asynchronous reset can cause issues in a synchornus system - Pipelining (open question) -definition of setup time and hold time -Techniques to reduce power consumption (open question)
Low power design, STA
STA, power analysis and optimization, asynchronous fifo, clock domain crossing,seq detector fsm, counter, other verilog problems, synthesis, minor verification qs, comp arch topics like out of order execution, tomasolu, cache,
I was also asked about why CMOS is used in implementing logic gates. Next, I was about sizing of transistors of a 2 input NAND gate.
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