Suppose you have a 4-bit shift register made using D-type flip flops with a positive Clock-to-Q delay and a hold time of 0. Is it possible for this circuit to have hold time violations? Why?
Asic Engineer Interview Questions
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What would be behavior of a CMOS inverter if the nMOS and pMOS are interchanged?
Design a circuit that would count 1 every time another counter counts from 0 to 255. One of the counter is working at higher frequency than the other.
(Unexpected) What the types of caches?
Suppose you discover that the circuit you are testing in the lab does not function correctly due to a hold time violation. What would be the first thing you try to make the circuit work?
Differentiate between = and => sings in verilog.
How do I connect two designs working at different clock speeds ?
Write the base-11 representation of the decimal number 175.
using a simple logic gate, convert a SET type flop to a RESET type flop
Suppose you have an infinite bit stream representing a binary number (LSB first), and that stream is entering your machine one bit per clock cycle, and you want your state machine to output a 1 any time the total is divisible by 5, otherwise output zero.
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