What are setup time and hold time?
Asic Engineer Interview Questions
1,315 asic engineer interview questions shared by candidates
Why OOPs is important
Static Timing Analysis questions.
Explain the last project
How does Cadence Encounter solve setup time violations before CTS
ASIC flow, setup/hold, fix violation
FIFO synchronized and asynchronized
They asked a lot questions on pipeline design. Like how to optimize the overall ipc regarding branch? Is it possible to get branch resolved in decode stage?
nothing in particular
round robin algorithm, scheduling? state diagram?
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