What are setup and hold time violations ? Showed me timing diagrams and asked me to explain the setup and hold times.
Asic Engineer Interview Questions
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setup/hold timing
Questions on the projects that I did and python progamming
They ask all basic questions about VLSI
They asked aptitude questions in the written test.
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Verilog code for shift register.
How to determine if a taped out chip failed hold/setup timing
They asked me to complete a complex Verilog design, including testbench covering all conceivable corner cases, and a PowerPoint about it. It was obviously impossible to complete in the time allowed, so clearly part of the interview is to find out who submits to slave labor without complaint. Details of the design question are protected by NDA.
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