Which is better, setup time or hold time violation?
Asic Design Engineer Interview Questions
1,316 asic design engineer interview questions shared by candidates
choose right cache strategy
What is a NAND gate
What are CDC and metastability?
Creating a unique list from a list with repeats
Write some codes to explain how to design asynchronous FIFO.
Launch 5 (t1,t2,t3,t4,t5) tasks in parallel, wait for 4 of the tasks to be done and kill the task t3.
Who does CPPR affect on a noise glitch
Are you interested in the position
Fifo depth calculation 80/10 and 8/10.
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