Black box CRC circuit checking...
Asic Design Engineer Interview Questions
1,315 asic design engineer interview questions shared by candidates
clock divider / mealy vs moor fsm / through my resume project / setup time hold time
Pipeline stuff
Garage door opener in verilog
1) FIFO RTL design 2) how to optimize power 3) steps to take ECO
virtual memory standard libraries in C how to build a cache how will you move data in cache what is recursion linked lists, binary tree, flat architecture, how a CPU would work
virtual memory standard libraries in C how to build a cache how will you move data in cache what is recursion linked lists, binary tree, flat architecture, how a CPU would work
I did get one or two questions about timing analysis and as a fresher i had almost no idea.
detailed test plan for a synchronous fifo
Wie würden Sie die Herausforderung lösen, wenn ein kritischer Timing-Fehler im finalen ASIC-Tapeout entdeckt wird?
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