How to debug a timing violation in the lab?
Asic Design Engineer Interview Questions
1,315 asic design engineer interview questions shared by candidates
They asked me questions related to Static Timing Analysis. For example, things like calculating setup time and hold time slack for a path in a digital circuit.
Digital design basics, UVM structure, OOPs
Basic Verilog code questions, such as latch inferences, correct assignations (not mixing blocking/non blocking), FSM, etc
CDC and related concepts. Clock main issues, metastability, glitching, etc, and the possible solutions
How to implement accumulators, multipliers in digital domain?
Interview questions were on core electronics concepts. Digital electronics mainly
Where do you see yourself in 5 years?
A module has 3 input and 5 output ports. Had a discussion for rest of the interview on that design. Basically the interviewer was trying to understand what I need to come up with a design. Like, do you a clock, what are you control signals, what is the functionality etc
Garage door opener in verilog
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