Write a C program which finds the missing card among a set of 51 play cards.
Asic Design Engineer Interview Questions
1,316 asic design engineer interview questions shared by candidates
c++ swap, pipeline
They asked me one question related to my project in verilog, that is how to make a digital clock using verilog in a FPGA board. They then asked me about counters and all. They also asked some questions related to CMOS, one question they asked from the OT and at last they asked me one brain puzzle.
Design a MUX using only NOT, AND and OR gates
What is clock domain crossing?
Constraint randomization based question linking to AXI and memory filling
Write the verilog code for a counter then change reset to asychronized.
Two questions： 1. 2 2bits comparators to 4 bits comparators, and reduce the delay to 1 units 1. data buffer like 0100000001, most simple rtl design to get the length (which is 9)
design sensor with minimal logic block
Write a Fibonacci number generator in Verilog, output a number in each cycle.
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