I applied online. The process took 1 day. I interviewed at Qualcomm (College Station, TX) in Sep 2016
Interview
I applied online and got the call for a phone screen very soon. The position was for a Digital Design Engineer. They were looking for person with knowledge in DSP.
Interview questions [1]
Question 1
Mostly on digital design like what is CDC and what are the stops to solve them.
Some questions focused on DSP concepts like a transceiver architecture, IIR and FIR filters, their relative advantages, disadvantages etc.
I applied through college or university. The process took 1 day. I interviewed at Qualcomm (Madgaon) in Aug 2016
Interview
I applied through the on campus placement program. They shortlisted around 15 students on the basis of technical plus aptitude test for interviews. There were three interview rounds. In the first round basics of programming, digital design and computer architectures were asked. Second round was a problem solving round on static timing analysis and Finite state machines. Third round was HR round where they grilled on my resume.
Interview questions [1]
Question 1
What are glitches. How would you get rid of them in a digital signal?
I applied online. The process took 2 months. I interviewed at Qualcomm (Raleigh, NC) in Mar 2015
Interview
Phone interview followed by on-site three weeks later. They were designing their own transaction protocol based on the AMBA AXI/ACE spec. I was fortunate to have studied the same for two months for directed research under a professor. I could tackle AXI questions. Interview went well. Didn't nail it but not too bad. Got a verbal offer three weeks later. Got the formal letter 1.5 weeks after the verbal.
Few details:
1. Had interview with three panels consisting of 2-4 members each.
2. Questions on bus architecture, synthesis, protocols, verilog, and certain design problems.
3. 1 major design question by each panes, takes 15-20 mins to solve; related to logic design--flip-slops, decoders, etc.
Interview questions [3]
Question 1
What are the channel in AXI and ACE? What is cache coherency?