• Support RTL design (VHDL, Verilog) of digital blocks and their system level integration
• Closely work together with RTL2GDS flow experts to optimize digital blocks and support block implementation
• Support chip and block level functional verification
• Implement and maintain regression setups for verification
• Create verification plans and develop verification environments based on Unified Verification Methodology (UVM)
• Support product qualification, testing and ramp-up
• Support methodology team with proposals and implementation of flow and methodology enhancements

Requirements:

• Bachelor’s/Master’s Degree in Electrical Engineering or Information Technology or similar
• Basic knowledge of hardware description languages (VHDL, Verilog) and System Verilog
• Knowledge about synthesis constraints (SDC) and UPF
• Understanding of UVM/OVM concepts and usage or strong motivation to learn concepts for state of the art verification
• Experience in functional verification and creating test concepts and verification environments is a plus
• Self-driven and hands-on way of working
• Good written and oral communication skills in English
• Team-player

Location:

Dresden, Germany
Duisburg, Germany

Employment Type:

Full-time (up to 40 hours per week)

About us:

Racyics® is Europe’s leading design service provider for mixed-signal system-on-chip design and turnkey ASIC services in advanced nodes.

We deliver professional analog, digital and mixed-signal design services tailored to the customers’ needs with focus on realization of complex System-on-Chips in leading edge technology nodes. Our team of more than 150 employees covers the complete chip design process up to system architecture development. Racyics is working for major German and international semi-custom companies both as a service provider and in collaborative partnerships.

Working at Racyics comes with many benefits, including flexible working hours, mobile work, a financial contribution to your childcare costs and great team events..