set up time and hold time
Vlsi Engineer Interview Questions
303 vlsi engineer interview questions shared by candidates
Basics of C language, Detailed explaination of projects
Basic vlsi questions , project questions
How do you replace cat with dog in perl?
What happens if you don't give a default statement? How is latch inferring bad for the design?
they asked about the asic flow, physical design steps, went a bit deep into those. then asked about STA and questions related to the projects done.
whats rtl level designing in verilog
All STA, Physical Design, timing power optimization questions. C++ , perl knowledge required
Using MUX to build up a AND gate
What is MAC/PHY?
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