Design an FSM for an elevator, different kinds of coverage, describe some RTL bugs you found in your current role, describe UVM testbench, how are sequences and drivers connected
Verification Specialist Interview Questions
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FIFO depth, and ASYNC FIFO test plan
pseudocode for factorial and think of cases that would fail it, they had given me a scenario and to assess it. A design was given and was asked to identify bugs in it.
difference between latch and flipflop?
Prepare a testbench. (Write in Verilog on the board)
digital, sv, uvm, verilog, scripting basics
Questions on pipelining
register vs flip-flop
What is stuck at fault, transition fault, bridging fault?
1. Programming questions like Fibonacci series. 2. Some questions related to Perl Programming. 3. Some questions on state machine design. 4. Synthesizable and non synthesizable constructs in Verilog. 5. Be thorough with the stuff on the resume.
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