Assertion to check the waveform
Verification Specialist Interview Questions
3,719 verification specialist interview questions shared by candidates
Look at these two statements: x, y are real finite number for all x, there exists a y such that y >x there exists a y such that for all x y >x 1) What is the difference between the two statements? 2) Do you think they are wrong ? Why ?
1. What are the pros and cons of adding an extra stage in a CPU 2. Follow-up: How does adding a stage affect the setup time and hold time
FIFO implementation Coding problem Asked about project i did
implementation of driver class based on the figure they gave
Discussed about verification projects in resume, how is formal and functional verification different. On coderpad, he gave an RTL code and asked to identify different scenarios and write SV properties of them. The RTL had a buggy FSM and asked me to debug it.
Create xor from mux. And create a state mechine
Explain encapsulation, inheritance, polymorphism. How does a TLB work and why is it necessary?
What would you use a modport for?
Cache Coherency, UVM and TLM related, SV concepts, Past projects.
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