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Verification Manager Interview Questions
3,718 verification manager interview questions shared by candidates
set up time, hold time
Describe your previous work experience
-Questions about cache coherency -Basic Verilog Questions -Questions about c++ and traversing trees
Build a NAND gate using the given logic gates, A and B. they have truth tables shown here:
I was asked about basic C++ knowledge, such as encapsulation and polymorphism. I was also asked to interpret some assembly code. A design manager asked me conceptual questions about computer systems and architecture, such as cache and virtual memory.
Questions were from resume. How will you verify a 32 bit ALU unit having 2 inputs is working fine for all 2^32 * 2^32 combinations?
Verilog questions and digital circuit designs
Out of order processor, importance ILP (and it's advantages), Digital design (realizing basic gates with a MUX)
Design an FSM for an elevator, different kinds of coverage, describe some RTL bugs you found in your current role, describe UVM testbench, how are sequences and drivers connected
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