How comfortable are you handling 100+ different components a day?
Verification Manager Interview Questions
3,719 verification manager interview questions shared by candidates
Design Nand Gate using CMOS?
The first round had questions based on signal processing, basics of system Verilog, and I was given a take-home coding task to write an RTL code to check if there is an increment, decrement by 1 bit and if not, print error; and verify the same using a class-based testbench.
What classes did you like/dislike?
Do you know object-oriented code?
Where do you see yourself in 5 years?
resume.
Question regarding Logic design, Verilog ,State Machine- pattern detection, Comp Arch- Pipeline, hazards, cache, associativity, Basic Perl were asked.
if I talk to your previous boss, what he/she/they gonna say about you?
model ADC in verilog, how to find frequency of a signal in verilog
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