Digital, Verilog, System verilog, UVM,Linux commands
Verification Manager Interview Questions
3,712 verification manager interview questions shared by candidates
concepts of UVM
sv, uvm and projects
they explained few scenarios and they are asking to write assertions for that
blocking vs non-blocking statements in sv
Types of memory and difference between memory and register, register, RAM, ROM, 64 bit adder, 64-bit register, OSI layer, Physical layer, interrupts, Types of interrupts, why it is priority high for non-maskable interrupts, why it is priority low for maskable interrupts, latch and flipflop. how latch acts as memory, many qns like these
What do you know about your job
What are the ways to synchronize signals and busses?
Why you want to work at Blinq?
How the data transfer will happen between a DRAM and Main Memory and some more questions related to Processor design.
Viewing 231 - 240 interview questions