Some question related to accessing analysis ports in a sequence ( via sequencer)
Verification Interview Questions
3,718 verification interview questions shared by candidates
Difference between verilog and sv.? Basic interface questions.
Asked about project details and uvm sv concepts
who do I know at Micron who can refer me to get the job without
How will you verify this circuit ? ( A black box)
Previous project based questions Work Motivations Basic Engineering questions like Wireless technologies, SMPS, Power consumption etc
1. Constraint random, assertions, UVM env 2. OOPS concept 3. Coverage, python scripting 4. Verilog and digital logic
FSM for sequence detector. Verification environment. Verilog programming.
How to set config_cb from lower to higher hierarchy
I can't say exactly but one SystemVerilog question was to implement a finite state machine given a certain output. Review sequence detectors.
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