Design, Test plan, SystemVerilog ......
Verification Interview Questions
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how to resolve the issue with a malfunctioning vending machine with a pending deadline
- More details about projects and experiences on the resume - 3 questions DSA related to embedded systems (only walking through ideas)
Questions on writing constraints for the given sequence.
System Verilog Assertions- FIFO Based
We want to send a specific amount of data and to prevent errors, we want to divide the data into several segments randomly within a certain size range. How can we perform this division so that there will definitely be enough data for all the remaining packets?
first was an assembly question, to implement multiplication with certain commands and few registers avaliable. second question was to build a xor gate with 4 wierd components which are sometimes Z and sometimes have output.
1)data should be <20, this was the constraint existed, but you should make the data in range 30 to 40 without using constraint_mode. 2) what the uses of bins in coverage
show how to access an address in cache and implement it.
Had to write a verilog code for some handshaking protocol.
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