SystemVerilog basics and UVM basics
Verification Engineer Interview Questions
3,716 verification engineer interview questions shared by candidates
Why are you interested in working with Intria?
1. Explain your minor project. 2. They focused on Digital Electronics and Verilog coding skills 3. Aptitude questions 4. Some computer architecture questions
Why are you choosing VLSI?
dld, verilog, sv, uvm, protocols
None. Read a script.
Asked for my understanding of the role - it is worth researching the company well beforehand as i felt perhaps underprepared for this question in particular.
What are the problems you faced when interacting with the client?
what is the flow of UVM methodology, and structural view of verification ?
related to the offered role skills
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