They asked me about my expertise and skills relevant to the position.
Verification Engineer Interview Questions
3,718 verification engineer interview questions shared by candidates
Digital logic and C programming questions
They mostly concentrated on sv , uvm
A lot of technical questions relating to logic design, timing and IC design. Also a lot of questions about what I had worked on in the past.
not many hard questions. hardest had to be "how are you at work?"... very open ended question. they seemed to want me to either really praise myself or really berate myself
Regarding Technical skills I don't have any difficulties and regarding job location to change from Bangalore can be difficult
Nothing of that sort
not much difficult
Mostly SV and methodology based and also previous projects.
Write the VHDL or Verilog code for a given state machine diagram.
Viewing 3191 - 3200 interview questions