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Verification Engineer Interview Questions
3,718 verification engineer interview questions shared by candidates
Was asked about basics of computer architecture, Digital Design and verilog
They asked about uvm fundamentals. They were looking for strong uvm experience and asked me to write code for scoreboard, monitor and asked about how to connect them.
Medium assertions questions. They were related to grant
How weird are you? I'm not joking
Explain how an out-of-order processor works? How do you implement register renaming? Difference between an architectural and physical register file
General resume questions
difference of Union and Struct (C++). VIPT cache.
How to do the formal verification for a given module
pipeling and harzard.
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