What is an Agent? Passive vs. Active.
Verification Engineer Interview Questions
3,719 verification engineer interview questions shared by candidates
what is Synchronous reset and asynchronous reset?
Abstarct class vs Interface, inheritance,polymorphism…..etc Observer and Factory DP in details. Log file output analysis. Behavioural questions. Giving basic and simple designs with some specifications and elaborate a strategy to verify it.
what is function overriding and overloading
Describe your experience/elaborate on projects on your resume
What did you learn from your Digital Logic and Computer Organization course?
Q 1 What will happen if you drive different sequence item other than the registered one ?
Draw the circuit base on the coding provided
Difference between Verilog and SV. Difference between blocking and non-blocking. Inheritance and virtual functions. Many C codes such as reverse an array, reverse bits of a number, get all even bits of a number, Fibonacci series, generate a random floating point number between a and b, Find a number in an array for which sum of all elements to its left= sum of all elements to its right. Few questions on digital logic such as finding minimum gates required for a given truth table, sequence detector, generate AND gate from 2 input mux etc.
Interviewer gave me two lines of code of value swapping which includes one blocking instruction and one non-blocking instruction with some delay and asked me output.
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