Asked about design project experience.
Verification Engineer Interview Questions
3,719 verification engineer interview questions shared by candidates
-how do you keep yourself motivated? -tell me about a weakness you have -tell me about a mistake you've done and many more.
Tell me about yourself and your skills
Explain what you learned in this course (VHDL, design classes, object oriented programming, etc)
1. Describe your current project, contribution and team structure? 2. Write Read and write transactions timing diagram of APB bus. With and without wait states? 3. Find the second largest in the integer array with single iteration. 4. Given a character array of 1000 elements, how do you find, how many times each of the character is repeated? 5. If there is any digital wave coming with random 0s and 1s, how do you find the time difference between 2 successive 1s? 6. Write full & empty conditions for FIFO. What are the verification scenarios of Asynchronous FIFO. 7. Behavioral questions related to personality and team.
Questions related to what you have mentioned on your resume. Digital concepts, FSM related questions, basic Setup and Hold time questions. I was asked a lot of general coding questions, SystemVerilog questions.
Walk me through your resume?
Where have you used your data analytics skills?
Basics of SV and UVM. Few more depending on your experience, based on you previous projects(if any).
Asking abut the technical question.
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