What is TLB cache? Why is it used?
Verification Design Engineer Interview Questions
3,720 verification design engineer interview questions shared by candidates
A general question that sees how is my verification thinking. Since I had no previous experience with verification, it took my a little while to understand what was asked.
Questions about past experience with Verilog and VHDL
Why modport is used? What is polymorphism? What is deep copying ? what is inheritence? Why we are writing interface? Different Phases in UVM? Which phase are task and which are functions?
It was a quetion about linked lists.
It was a quetion about pysical memroy.
system verilog constraints interview questions
build state machine for "CAFFE" case
Reverse a string and return it.
My projects which was relevant to job role
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