Definition of sta and pd design flow
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Did u work on proof point. ?
Static Timing Analysis and its tools used
Solving k-maps, coding latch vs flip flop in VHDL/verilog, problems in placement and routing, how to resolve layout issues like drc's
Knowledge of Coding (Not extensive- Basic) Where do you see yourself in next 5-10 years?
Mapas de Karnaugh. Manejo de memorias.
Questions about debug of failure
PD concepts, Timing, STA, Extraction, RTL design
Tell me about your prior work experience in how it relates to this
How to handle zero day attack
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