Why does the PCIe spec limit the time skew of a common clock architecture to less than 12 ns skew between the clock routed to the transmitter side and the sum of the clock routed to the receiver side PLUS the routing length of the TX lane to the receiver.
To tell them about my most recent projects
Can you describe a challenging signal integrity problem you encountered in a previous project and how you resolved it?
.Transmission line theory
A differential pair is routed as a microstrip and the weave of the FR4 causes the er on one of the signals in the pair to vary a lot from the other member of the pair (think egregious, 3.4 on one, 4.5 on the other). What effects can you expect and what can you do to mitigate.
Details on a PLL - loop bandwidth filter selection choice and detailed technical explanation.
Lots of questions about stackups, and how you would advise designers early in the design process to avoid SI and PI issues
What is the most important figure of merit with signal integrity?
How much CAD do you use from day to day basis? Goes over and questions your resume
All sorts of questions. One interviewer has a full list of 20+ questions to blast thur. Didn't seem to care how and what I've done from my past job experience.
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