Verification of the DUT
Senior Verification Engineer Interview Questions
189 senior verification engineer interview questions shared by candidates
systemverilog basics and UVM basics
They asked about the design verification process, UVM concepts and coverage.
Explain inheritance, polymorphism. Write test bench for sequence detector
Can we override constraints like data members?
Why do we need a virtual interface?
Difference Between Associative array and Dynamic Arrya
Merge two linked lists
Write a function to find the largest and second largest element in an array ( without using sorting)
Describe the system you were verifying in your previous role
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