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Senior Verification Engineer Interview Questions
189 senior verification engineer interview questions shared by candidates
Write top level test bench that sets up he virtual interface
Some question related to accessing analysis ports in a sequence ( via sequencer)
My previous experience, as well as a few mock examples related to verification and what my process would be
What is the terminal command for checking the list of active processes? What is the terminal command for checking the amount of free disk space? What does the '-x' parameter do for the `bash` command? Have you used Docker? Have you used KVM?
FSM for sequence detector. Verification environment. Verilog programming.
How to set config_cb from lower to higher hierarchy
Give a detailed example of a test you wrote
How to design a UVM testbench for a given design. What all componets are needed etc. Corner cases to test out and efficient way to build environment
First round: 1) Introduction on your experience, the job profile requirement and your motivation. DIscussion our application and CV. Second Round: 1) Technical questions on the projects you worked on. This will be in details. Both simulation based ( SV/UVM) and formal methods were discussed. Third round (HR): 1) very generic HR questions like, tell me about your self, your strengths/weakness, motivation to join Synopsys, what your team will say about you . describe a conflicting situation you handled, how do you keep your team motivated, salary expectations and personal situation etc.
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