sorting, RTL coding, perl, C, C++
Senior Design Engineer Interview Questions
1,076 senior design engineer interview questions shared by candidates
UVM methodology related question about 1. Virtual interface 2. Fork join 3. UVM create and resource_db() usage. Some questions on Code coverage closure. I was asked to write c/sv code for cdc fifo and build a verification environment around it and simulate fifo full and fifo empty conditions
Skillset: CPU Architecture, ISA knowledge, Digital Design, FSM design
What are the different pipelining stages and related
How many gates in the critical path of a Carry-look-ahead adder?
What are the pipeline stages in a state-of-art microprocessor?
Describe the I2C interface Verilog code and the use of tristate buffers while making an I2C master module. Describe what is CAS latency
Who are you and what you did?
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