1. Given a set of specifications for register elements , how do we compute the maximum frequency of operation? 2. What are the different types of constraints used in design , when and how are they specified?
Rtl Design Interview Questions
272 rtl design interview questions shared by candidates
1. Counters 2. CDC and type of Synchronizer 3. Sync FIFO
Basic RTL codes and degital design,fsm state digram(melay andMoore state machine).setup and hold time.latch and d flip flop.synchronous vs asynchronous fifo.syncronohs reset and asynchronous reset verilog code .static timing analysis
About counter and asked to design them
how to you put synchronous and asynchronous reset in your code? what is the pros and cons of both situation.
how do you perform floating point addition in hardware?
If the incoming data to the FIFO is 1Mhz and outgoing data is at 1Khz and the data is 32 bits wide, what would be the depth of the FIFO?
How is organized a CPU?
What's the 2 principle of Cache.
State Machine design , SRAM basics
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