related to RTL and UVM
Rtl Design Engineer Interview Questions
272 rtl design engineer interview questions shared by candidates
There really isn't anything unexpected, the HR questions are also really standard and no tricky question like your weakness or how to deal with someone who is hard to work with.
General system design, general CDC questions, questions on experiences,
FIFO, One Aptitutde question also.....
Questions about hold and setup time, basic digital logic questions
How can you avoid the setup violation from the given circuit?
Basics of digital electronics, VLSI related concepts and Verilog coding related questions and Resume based question on the projects.
SRAM related questions, Verilog coding, FSM
How/what do you do at RTL level to meet timing in Synthesis with example?
Introduce yourself 5 pipeline stages, the type of hazard. how to solve structural hazard, insert NO. of bubbles to solve the data hazard linked list and pointer basic knowledge.What's your plan in 10 years.
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