Questions covered computer architecture, timing problems, power analysis, and design problems
Rtl Design Engineer Interview Questions
272 rtl design engineer interview questions shared by candidates
Self intro, basic definations in CTS and STA, low power design methodologies, local vs global skew, problems on sta
Describe clock domain crossing techniques
Async fifo design and SDC contraints for it. Pulse synchronizer cross clock domains.
Based in UVM and System verilog and project related questions
Lots of questions on OoO processor and Caches Learn more than what is given in your coursework
ASIC design processes, techniques, design processes
Asked me to draw a boolean expression using only NAND gates.
latch vs FF
Basics of digital K map based questions Verilog programing some logical ability questions
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