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2,451 product validation engineer interview questions shared by candidates

1. assertion in system verilog 2. differences on task and function in system verilog 3. CMOS problems. 4. Capacitors are connected in series and parallel problems. find total capacitance, charge and voltage across the capacitors 5. What are generator clocks 6. diff between reg, wire and logic 7. detail on blocking and non blocking assignment 8. Inheritance concept in system verilog and how do you implement it 9. Explain full adder truth table (Please explain in words, I did a great blender by explaing line by line with numbers 10. virtual interfaces 11. how do you implement syncronous reset and asyncronous reset 10.
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Logic Validation Engineer

Interviewed at Intel Corporation

3.9★
Nov 19, 2019

1. assertion in system verilog 2. differences on task and function in system verilog 3. CMOS problems. 4. Capacitors are connected in series and parallel problems. find total capacitance, charge and voltage across the capacitors 5. What are generator clocks 6. diff between reg, wire and logic 7. detail on blocking and non blocking assignment 8. Inheritance concept in system verilog and how do you implement it 9. Explain full adder truth table (Please explain in words, I did a great blender by explaing line by line with numbers 10. virtual interfaces 11. how do you implement syncronous reset and asyncronous reset 10.

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