it was general discussion about logic design and he gave me discribtion about circuit and asked me to leocate the signals that i should select for testing and verifying they gave me small task about an alu and i am supposed to write verification code in system verilog for it , actually they were very generous they provide the matrials to learn more about system verilog and how to write such a design
Mostly from you CV. 1. Explain the testbench architecture. 2. GLS exerience 3. vManager regression 4. Formal verification.
Verilog code for D-flip flop
Tips for round 2- keep your basics strong. Don't need much. Just got get played by interviewers. If you're stuck or don't know the answer. Atleast try for an approach and keep asking for feedback. Before solving any question, explain your approach and then proceed. Your behaviour shouldn't be like digital systems, either 0 or 1. It should be like analog. Keep explaining every step. And don't say anything that you can't explain. Tips for round 3- Just don't lie. Speak the truth. Don't mention GATE scores in CV. Deny any further studies plan from your side. Just say that you'll do it if your firm wants you to upgrade your skills and be more productive for firm. Else you have no plans. Preferred location - Always say Noida.
3. What is FIR filter? Impulse response of a system?
what is setup and hold time?
Generate a clock divider using or gate
RC circuit, Integrator differentiator, SystemVerilog, Digital circuits & STA
Offered coding questions on the spot at the last ten minutes of the interview.
-General digital flow design -General UVM verification questions
Viewing 61 - 70 interview questions