On-campus: Verilog code writing, simple hardware design question using muxes and counter that was approached from different levels of abstraction. Phone Interview: Entirely computer architecture questions, including cache coherency protocols, cache organizations
Q. Describe your test plan for a FIFO
Sv and UVM project knowledge protocol mentioned in CV
How to implement a priority encoder in Verilog?
setup/hold time ;verification coverages and types
Tell us more about your work at "A." How would you verify something? How would you go about writing a protocol and timeless for a project?
UVM, components, monitor, driver, constraints
Linux: how to create a file, how to find all file that contain FOO, with case sensitive and case insensitive.
evaluation regions semaphore virtual interfaces modport uvm
How would you describe Functional Verification
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