Tell me about your self do you have any projects of yours
Design Verification Engineer Interview Questions
3,710 design verification engineer interview questions shared by candidates
Basics of sv, sva, verilog
It was a quetion about linked lists.
It was a quetion about pysical memroy.
How to convert hexadecimal to decimal.
Design a circuit that takes 4 bit BCD as input and has the input times 5 as output
Draw a NAND using cmos gates
system verilog constraints interview questions
MESI Protocol FIFO Verilog and condition for full and empty Build FSM for 20 story building elevator (you have control in elevator and controls on every floor and discuss what floors take priority Build a clock divider to take 2MHz signal to 1MHz Build a 4:1 MUX using behavioral verilog than structural verilog Tell me how many bits per tag, offset, and addr based on cache structure (1MB 8 way associative) Tell me 5 stage pipeline Tell me about different hazards and explain types of data hazards how would you go beyond 5 stage pipeline
The most unexpected question was about prior negative job experiences and how I reacted to them. Since I had had several such experiences during 21 years of being a pharmacist, this question was not difficult to answer.
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