What do you expect to do when you work here?
Design Verification Engineer Interview Questions
3,713 design verification engineer interview questions shared by candidates
What my previous job experience has been and what are my areas of expertise?
They asked me to sort an array with an specific condition, without sorting
Define verilog ,systemverilog. Memory /cache
I didn't experience anything that was not expected in some way.
What are your greatest strengths and weaknesses?
Write a function that creates a randomized array of integers from 1 to 100, each number appearing once.
SV, UVM and Digital Electronics Questions.
Do you have high speed internet. What are your qualifications as far as working multiple applications. Do you have open availability. Will you be able to not miss any days during training.
Why did you choose Scotiabank
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