Q. What are all run-phases and in detail discussion about it Q. Basic constraints related to dist, and assertion
Design Verification Engineer Interview Questions
3,719 design verification engineer interview questions shared by candidates
What would you use a modport for?
Look at these two statements: x, y are real finite number for all x, there exists a y such that y >x there exists a y such that for all x y >x 1) What is the difference between the two statements? 2) Do you think they are wrong ? Why ?
1. What are the pros and cons of adding an extra stage in a CPU 2. Follow-up: How does adding a stage affect the setup time and hold time
Create xor from mux. And create a state mechine
Computer Architecture, Coding in SystemVerilog
write HDL code for a FSM
cache coherency related like MSI
FSM, SystermVerilog, and software leetcode related questions.
Explain encapsulation, inheritance, polymorphism. How does a TLB work and why is it necessary?
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