What is your productive skill
Design Rtl Interview Questions
272 design rtl interview questions shared by candidates
Write verilog code,difference between gate and latch,demonstrate difference between asynchronous and synchronous reset using waveform,what is a gitch
Explain each state in a mesi protocol.
Know the 5 stage pipeline well
Software (OOP, efficiency, data structures), Computer Architecture (cache coherency, pipelining), Logic (k maps, simplifying boolean expressions), and Verification (coverage, how to test, previous experience)
What is blocking and non blocking statement
Difference bw asynchronous and synchronous circuits Propagation delay Static and dynamic delay
What do you understand by low power design ? Can we use Verilog to design a low power system ?
What is metastability, and how would you prevent it?
Experience in writing RTL in the past Some hands on RTL writing
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