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There were some general questions related to my projects and my experiences. Some technical questions that I can remember are: 1) Given a diagram of some basic arithmetic operations and asked to simplify it. Basically, you try to reduce the area by utilizing one less multiplier. A follow up question was given the latency for each operation and ask how to improve the latency. The answer is basically to pipeline the combinational circuit by using flip flops to split into to stages. 2) A basic timing question regarding the max frequency the flip-flop can operate at given the various D-Q, C-Q, hold and t-combination timings. Then a follow up question asks if one of the time is changed, how would it affect the circuit. Basically the answer is to reduce the frequency to allow correct operation. Another follow up was if the hold time is not satisfied, would changing the clock frequency help. The answer to that question is no and to get that answer you need to draw the timing diagram and see that changing the frequency does not help. 3) Another question involving multiple flip-flops and asked to draw timing diagram of various points in the circuit. 4) A buffer over-flow problem and how to solve it. Basically, you had to figure out that the input side of buffer is writing at a higher rate than the reading side of the buffer. Basically, you had to delay the sending function for a period of time after sending certain amount of packets of data.
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Hardware Design Engineer

Interviewed at Evertz Microsystems

3.1★
Apr 11, 2013

There were some general questions related to my projects and my experiences. Some technical questions that I can remember are: 1) Given a diagram of some basic arithmetic operations and asked to simplify it. Basically, you try to reduce the area by utilizing one less multiplier. A follow up question was given the latency for each operation and ask how to improve the latency. The answer is basically to pipeline the combinational circuit by using flip flops to split into to stages. 2) A basic timing question regarding the max frequency the flip-flop can operate at given the various D-Q, C-Q, hold and t-combination timings. Then a follow up question asks if one of the time is changed, how would it affect the circuit. Basically the answer is to reduce the frequency to allow correct operation. Another follow up was if the hold time is not satisfied, would changing the clock frequency help. The answer to that question is no and to get that answer you need to draw the timing diagram and see that changing the frequency does not help. 3) Another question involving multiple flip-flops and asked to draw timing diagram of various points in the circuit. 4) A buffer over-flow problem and how to solve it. Basically, you had to figure out that the input side of buffer is writing at a higher rate than the reading side of the buffer. Basically, you had to delay the sending function for a period of time after sending certain amount of packets of data.

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